DFT Team Manager

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Job Description:

DFT Manager

Broadcom's ASIC Product Division is seeking candidates for a DFT management position at our Austin, Texas Development Center. The successful candidate will be responsible for leading the local DFT team to execute programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required manage the DFT team through various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure, and acting as a primary point of contact for the customer and internal executive management. It's also an expectation of the role that some hands on work will be required, in order to support the activities of your assigned DFT leads.

Responsibilities:

• Understanding Broadcom and customer DFT feature requirements and DPPM goals & defining appropriate DFT specifications for the ASIC
• Managing the team to implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
• Working closely with STA and DI Engineers design closure for test
• Project managing DFT the resources assigned to you
• Driving silicon failure analysis, diagnostics and yield improvement efforts
• Interfacing with the customer, physical design and test engineering/manufacturing teams located globally
• Working closely with I/P DFT engineers and other stakeholders
• Adopting a line manger role for your staff, including performance management, coaching, career development and administrative tasks

Skills/Experience:

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
• Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6
• Basic knowledge Test-STA and constraints
• Strong background on IEE1687, IJTAG, ICL and PDL
• The ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug, root cause analysis and communication skills
• Experience working on Tessent SSN is highly desired

Education & Experience:

• Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience, with a minimum of 3 years in management

Compensation and Benefits

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

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