SoC Physical Design Formal Verification Engineer, HBM

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As an SoC Physical Design Formal Verification Engineer in the Heterogeneous Integration Group (HIG), you will own the formal verification signoff of advanced HBM SoC logic/base die designs as they move from RTL through synthesis, DFT insertion, place-and-route, and ECOs to tapeout. You will work closely with RTL design, physical design, DFT, low-power, and STA teams to ensure every implementation step preserves functional intent and power intent. This is a hands-on role with opportunities to own block and full-chip formal signoff and shape formal methodology across multiple product generations.

Key Responsibilities

• Own formal equivalence checking (LEC) for HBM SoC blocks and full-chip across the implementation flow, including RTL-to-netlist, netlist-to-netlist (post-synthesis, post-DFT insertion, post-CTS, post-route), and ECO netlists.
• Develop and maintain robust equivalence setups, including handling of retiming, clock gating, multibit banking, constant/unreachable register optimization, scan and MBIST insertion, and black-boxed hard IP.
• Debug and resolve non-equivalence and abort points efficiently, partnering with RTL, synthesis, DFT, and physical design teams to root-cause issues and converge designs to clean signoff.
• Perform static low-power verification (e.g., Conformal Low Power, VC LP) against UPF power intent, covering isolation, level shifting, retention, power switches, and always-on connectivity through implementation.
• Drive functional ECO generation and implementation using formal ECO tools (e.g., Conformal ECO, Formality ECO), minimizing patch size and physical impact late in the design cycle.
• Run and review netlist-level structural and formal checks such as CDC/RDC, X-propagation, and connectivity checks as required by signoff criteria.
• Define formal verification signoff criteria, checklists, and QoR metrics, and represent formal verification status in tapeout readiness reviews.
• Build and improve automated formal verification flows and regression infrastructure using Python, TCL, and shell to improve runtime, capacity, and debug productivity.
• Collaborate with EDA vendors to resolve tool issues, evaluate new capabilities, and adopt best-in-class methodology across product generations.
• Develop agentic AI flows based on latest LLM and Gen-AI capabilities.

Required Qualifications

• Strong hands-on experience with formal equivalence checking on complex SoC designs at advanced process nodes.
• Proficiency with industry formal verification tools (e.g., Cadence Conformal LEC/LP/ECO, Synopsys Formality/VC LP, Siemens Questa or equivalent).
• Solid understanding of the RTL-to-GDSII implementation flow, including synthesis, DFT insertion, placement, CTS, routing, and ECO flows, and how each step impacts equivalence.
• Experience debugging non-equivalence, aborts, and setup issues caused by synthesis optimizations such as retiming, register merging, clock gating, and multibit flops.
• Working knowledge of power intent (UPF/CPF) and low-power design concepts, including isolation, level shifting, retention, and power gating.
• Familiarity with DFT structures (scan, compression, MBIST, JTAG) and their treatment in formal verification.
• Good understanding of Verilog/SystemVerilog and gate-level netlists, and ability to read and reason about RTL and synthesized logic.
• Proven tapeout history on advanced foundries (e.g., TSMC) and understanding of full-cycle SoC development flows.
• Strong scripting/automation skills using Python, TCL, Perl, and/or shell.
• Ability to work in a global, cross-functional environment with strong communication and debugging skills.

Preferred Qualifications

• Experience with HBM / DRAM adjacent SoC designs, or memory-subsystem-heavy SoCs.
• Experience with functional ECO generation and implementation on large hierarchical designs.
• Exposure to property-based formal verification (SVA, formal apps) or netlist-level CDC/RDC signoff.
• Familiarity with physical verification and signoff concepts such as DRC, LVS, and STA.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 7 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

The US base salary range that Micron Technology estimates it could pay for this full-time position is:

Additional compensation may include benefits, bonuses and equity.
Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

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